A High Speed Low-Power Accumulator for Direct Digital Frequency Synthesizer

Author

Kim, Yong Sin ; Kang, Sung-Mo

Author_Institution

Dept. of Electr. Eng., California Univ., Santa Cruz, CA

fYear

2006

fDate

11-16 June 2006

Firstpage

502

Lastpage

505

Abstract

A high speed low-power 32-bit accumulator for direct digital frequency synthesizer (DDFS) is presented. The DDFS consists of a phase accumulator, a phase-to-sine amplitude converter, and a D/A converter. For accumulator design, high speed pipelining scheme is commonly used to increase throughput and to reduce power consumption. Our design decreases power consumption and the number of registers down to 24% and 37% of the conventional pipelined accumulator

Keywords

clocks; digital-analogue conversion; direct digital synthesis; high-speed integrated circuits; integrated logic circuits; low-power electronics; 32 bit; D/A converter; direct digital frequency synthesizer; high speed accumulator; high speed pipelining scheme; low-power accumulator; phase-to-sine amplitude converter; Clocks; Communication switching; Energy consumption; Flip-flops; Frequency synthesizers; Pipeline processing; Power dissipation; Power generation; Shift registers; Silicon compounds; accumulator; direct digital frequency synthesizer (DDFS); gated clock; low power; pipelining;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2006. IEEE MTT-S International

Conference_Location

San Francisco, CA

ISSN

0149-645X

Print_ISBN

0-7803-9541-7

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2006.249620

Filename

4014944