An Efficient Approach to Develop Secure Scan Tree for Crypto-Hardware

Scan chain based test has been a common and useful method for testing VLSI designs due to its high controllability and observability. However scan chains have recently been shown to pose security threat to cryptographic chips. Researchers have proposed various prevention architectures like scan tree followed by a compactor, locking and TAP architecture. But these solutions lead to huge hardware overhead and slow the process of testing. In this paper we propose a novel secured scan tree architecture which has very low gate overhead, high fault coverage and is amenable to fast online testing.