DocumentCode :
2710917
Title :
One chip 2fH up-converter for high end/HDTV TV receivers
Author :
Correa, Carlos ; Christopher, Todd ; Saeger, Tim
Author_Institution :
Thomson Consumer Electron., Villingen, Germany
fYear :
34851
fDate :
7-9 Jun1995
Firstpage :
44
Lastpage :
45
Abstract :
Presents a description of a one-chip up-converter architecture study, which performs a 1fH to 2fH, line-doubling, video up-conversion, for both 50 Hz-625 lines and 60 Hz-525 lines video systems. This architecture concept, the DMU (dual mode up-converter), converts the interlaced digital YUV video input signals into either a non-interlaced progressive 1 V field rate (50 Hz/60 Hz) or a interlaced doubled 2 V field rate (100 Hz/120 Hz) display format
Keywords :
digital signal processing chips; digital television; high definition television; telecommunication standards; television receivers; television standards; video signal processing; 1fH to 2fH line-doubling video up-conversion; 50 Hz; 50 Hz-625 lines; 60 Hz; 60 Hz-525 lines; DMU; HDTV TV receivers; dual mode up-converter; high end TV receivers; interlaced digital YUV video input signals; interlaced doubled 2V field rate display format; noninterlaced progressive 1 V field rate display format; one chip 2fH up-converter; up-converter architecture; Cathode ray tubes; Consumer electronics; HDTV; Liquid crystal displays; Motion detection; Noise reduction; Nonlinear filters; Plasma displays; Signal generators; TV receivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics, 1995., Proceedings of International Conference on
Conference_Location :
Rosemont, IL
Print_ISBN :
0-7803-2140-5
Type :
conf
DOI :
10.1109/ICCE.1995.517886
Filename :
517886
Link To Document :
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