Title :
Gated clocks in RT-synthesis and simulation
Author :
Ecker, Wolfgang ; Windisch, Andreas ; Mades, Jochen ; Schneider, Thomas ; Ke Yang
Author_Institution :
Infineon Technol., Munchen, Germany
Abstract :
The paper discusses several alternatives for dealing with the simulation mismatch resulting from partially gating clocks in RT-descriptions. Currently synthesizable approaches as clock delta balancing and simulation time delay of combinatorial assignments are first discussed. Local clock gate descriptions based on wait statements and global clock gate descriptions based on guards are then presented. Finally, an extension of the VHDL port map towards type conversion functions with more than one (signal)-parameter is proposed
Keywords :
clocks; hardware description languages; logic gates; real-time systems; virtual machines; VHDL port map; clock delta balancing; combinatorial assignments; gated clocks; global clock gate descriptions; guards; local clock gate descriptions; partial clock gating; real-time simulation; real-time synthesis; simulation mismatch; simulation time delay; type conversion functions; wait statements; Circuit synthesis; Clocks; Computational modeling; Delay; Hardware design languages; Logic; Postal services; Signal processing; Signal synthesis; Standards development;
Conference_Titel :
VHDL International Users Forum Fall Workshop, 2000. Proceedings
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-0890-1
DOI :
10.1109/VIUF.2000.890269
