Modified Smith Predictor Controller for Network Congestion Control

Reconfigurable computing is an emerging paradigm of research that offers cost-effective solutions for computationally intensive applications through hardware reuse. There is a growing need in this domain for techniques to exploit parallelism inherent in the target application and to schedule the parallelized application. This leads to the need for scheduling and mapping of tasks on to several hardware resources (Reconfigurable Logic Units). Here Reconfigurable Logic Unit (RLU) represents reconfigurable hardware module on a reconfigurable System-on-Chip (rSoC). This paper addresses the problem of scheduling and mapping of the tasks onto the RLUs for a given application task graph by introducing a new concept of parameterized modules and variable silicon area sizes. In contrast to existing algorithms, this paper considers heterogeneous RLUs that vary in terms of size of the chip area and multiple versions of implementations (configuration bit streams) for each task. As this is a new idea, here we are presenting algorithms which employ heuristics and dynamic programming methods to schedule tasks on to several hardware resources with the objective of minimizing the total execution time. The results show that dynamic programming algorithm always obtains the optimal or near sub-optimal scheduling list, whereas heuristic method is not providing always optimal /efficient scheduled list. The algorithms are implemented using SystemC environment to support hardware as well as software co-simulation. Our results show that developed algorithm using dynamic programming is more efficient in terms of hardware utilization without losing the performance.