DocumentCode :
2710967
Title :
Testing a procedural interface for conformance to a standard
Author :
Parvathy, Uma ; Martinolle, Françoise ; Subramanian, Swaminathan
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fYear :
2000
fDate :
2000
Firstpage :
91
Lastpage :
94
Abstract :
Procedural interface testing is a complex task since it requires in-depth knowledge in more than one domain. In particular, testing procedural interfaces (PI) to HDL simulators require knowledge of both programming and HDL modeling. This paper describes a methodology to automatically generate a test suite from a formal model specification of a HDL procedural interface. Since this test program is generated automatically from the formal model, it is correct by construction. Therefore an error encountered during the testing indicates either a problem in the PI implementation or in the formal model specification
Keywords :
conformance testing; formal specification; hardware description languages; program testing; software standards; HDL simulators; conformance testing; formal model specification; hardware description language; procedural interface testing; test suite generation; Automatic testing; Data models; Data structures; Hardware design languages; Navigation; Object oriented modeling; Runtime; Software quality; Software systems; Software testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VHDL International Users Forum Fall Workshop, 2000. Proceedings
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-0890-1
Type :
conf
DOI :
10.1109/VIUF.2000.890275
Filename :
890275
Link To Document :
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