DocumentCode
271110
Title
A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system
Author
Reyes, BenjamiÌn T. ; Paulina, German ; Tealdi, Lucas ; Labat, Emanuel ; Sanchez, Ricardo ; Mandolesi, P.S. ; Hueda, Mario R.
Author_Institution
Lab. de Comun. Digitales, Univ. Nac. de Cordoba, Córdoba, Argentina
fYear
2014
fDate
25-28 Feb. 2014
Firstpage
1
Lastpage
4
Abstract
A 12 parallel low voltage differential signaling (LVDS) transmitter fabricated in 0.13 μm CMOS is presented. Each LVDS channel can operate over 1.6 Gb/s and includes a programmable pre-emphasis circuit designed to reduce the data-dependent jitter (DDJ) caused by different lengths of PCB traces. Experimental results of the fabricated LVDS confirm the correct operation of the programmable pre-equalization circuit. The power consumption and area per channel is less than 20 mW and 0.084 mm2, respectively.
Keywords
data communication; digital communication; digital integrated circuits; integrated circuit design; jitter; logic design; low-power electronics; power consumption; programmable circuits; telecommunication signalling; CMOS LVDS transmitter; DDJ; LVDS channel; PCB traces; area per channel; bit rate 1.6 Gbit/s; correct operation; data-dependent jitter; low voltage differential signaling; power consumption; programmable preemphasis circuit; programmable preemphasis system; programmable preequalization circuit; size 0.084 mm; size 0.13 mum; CMOS integrated circuits; Copper; Delays; Power demand; Standards; Synchronization; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on
Conference_Location
Santiago
Print_ISBN
978-1-4799-2506-3
Type
conf
DOI
10.1109/LASCAS.2014.6820268
Filename
6820268
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