Compact floating-gate learning array with STDP

In this paper, we present a Spiking Neural Network (SNN) architecture that incorporates Integrate-and-fire (IF) type neurons and floating-gate transistors (FGTs) to store the synaptic weights. Compactness of the network has been the major target throughout the design. We believe that a CrossNet architecture lends itself very well to satisfy this goal. The synaptic weights are updated locally according to an approximation of Spike-Timing-Dependent Plasticity (STDP) rule. While the computations are performed internally in the analog domain the network is interfaced with a digital Address-Event-Representation (AER) to achieve robust off-chip communication. The operation of the array is described and selected simulations with 65 nm CMOS are shown.