Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets

Author

Seifert, Norbert ; Jahinuzzaman, Shah ; Velamala, Jyothi ; Patel, Nikunj

Author_Institution

Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA

fYear

2015

fDate

19-23 April 2015

Abstract

We report on muon-induced single event upsets (SEU) in SRAMs built on 32nm planar and 22nm and 14nm 3D Tri-Gate technologies. Experimental cross sections were measured using the M20C positive muon beamline at TRIUMF. Physics-based simulations were conducted to estimate sea-level SEU rates for both, positive and negative muons. Our results indicate that the muon induced upset rate is negligible compared to neutron induced upset rate, and the introduction of 3D Tri-Gate transistors reduced the susceptibility to muons by approximately two orders of magnitude relative to 32nm planar cross sections.

Keywords

SRAM chips; muons; radiation hardening (electronics); three-dimensional integrated circuits; 3D trigate transistor technology; M20C positive muon beamline; SEU; SRAM; TRIUMF; muon-induced single event upset; negative muon; physics-based simulation; planar technology; sea-level SEU rate estimation; size 14 nm; size 22 nm; size 32 nm; Acceleration; Atmospheric modeling; Life estimation; Mesons; Neutrons; Particle beams; Random access memory; Tri-Gate CMOS; accelerated testing; muon; planar; single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112676

Filename

7112676