An evaluation of accelerated failure time models of stress-migration and stress-induced voiding failures under vias

This paper extends a previously published model [1] of stress induced voiding (SIV) to the case where diffusion proceeds according to a power-law in the initial stress. The model is used to fit long-term, low-temperature (30°C) data from a 130 nm Cu/low-k BEOL process. In some cases, the data supports the use of a power-law void growth as evidenced by a “fattening” of the long-time tail in the failure statistics. The mechanisms for low-temperature power-law void-growth include: (1) dislocation creep from climbing dislocations within the Cu grains, (2) superposition of multiple stress-relaxation paths, and (3) statistical mixing of distributions. While statistical mixing is dealt with by stratifying the data by position on the wafer, it is not possible to separate the mechanisms of creep and multiple stress relaxation modes. The accurate assessment of the tail of the distribution is important for establishing the impact of scaling parameters on the reliability, in order to establish design-rules for zero failures due to SIV.