DocumentCode :
2711523
Title :
Parallel Logic Synthesis Using Partitioning
Author :
De, K. ; Banerjee, Prithu
Volume :
3
fYear :
1994
fDate :
15-19 Aug. 1994
Firstpage :
135
Lastpage :
142
Abstract :
In this paper, we present a partitioning approach of parallel logic synthesis, which is different from the previous approaches which involved parallelization of individual operations within the synthesis algorithm. We partition the given logic circuits and distribute the partitions to different processors for synthesis. For good load balancing, partitioning algorithm is tuned so that the estimated synthesis times of individual partitions are equal. To improve the quality of synthesized circuits, we propose a novel iterative repartitioning and resynthesis approach to parallel logic synthesis. Experimental evaluation in several large circuits are shown on a network of workstations, and results are compared with MIS.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing, 1994. ICPP 1994 Volume 3. International Conference on
Conference_Location :
North Carolina, USA
ISSN :
0190-3918
Print_ISBN :
0-8493-2493-9
Type :
conf
DOI :
10.1109/ICPP.1994.150
Filename :
5727846
Link To Document :
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