Mathematical Modelling and Simulation of a Buffered Fault Tolerant Double Tree Network

Many Interconnection Networks for large-scale multiprocessor computer systems have been proposed. Of them Multistage Interconnection Networks (MINs) compose a large subset. Multistage Interconnection Networks (MINs) are used to connect processors and memories in large scale scalable multiprocessor systems. MINs have also been proposed as switching fabrics in ATM networks in future broadband ISDN networks. A lot of research and development is reported in the area of Multistage Interconnection Networks of regular architecture, but Multistage Interconnection Networks of irregular architecture are largely ignored. Fault Tolerant Double Tree Network is a Multistage Interconnection Network of irregular architecture. In this paper a new mathematical model is proposed for performance evaluation of the buffered Fault Tolerant Double tree packet switching network under uniform traffic condition. An algorithm to implement this model is also presented and results obtained are compared with the results of simulation. It is shown that as the size of network increases, throughput decreases and delay increases.