Narrow width effects in CMOS n(p)-well resistors

Since the CMOS processes scale down till half submicron, even the use of n(p)-well resistors may become critical due to the interaction between the small geometry and the depletion width. In this work we present a model for n(p)-well resistor that takes into account the effects of temperature variation and resistor biases on narrow width structures. The model is obviously based on free parameters that become characteristic of the particular used CMOS technology and it can be implemented in advanced circuit simulators