• DocumentCode
    2711832
  • Title

    Characterizing the mismatch of submicron MOS transistors

  • Author

    Lovett, S.J. ; Clancy, R. ; Welten, M. ; Mathewson, A. ; Mason, B.

  • Author_Institution
    Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland
  • fYear
    1996
  • fDate
    25-28 Mar 1996
  • Firstpage
    39
  • Lastpage
    42
  • Abstract
    A test structure is presented to characterize submicron MOS transistor mismatch. The structure reveals the potential to improve matching by up to 300% without changing layout area. An expression is derived and verified by experiment which predicts the W/L geometry that gives optimum mismatch
  • Keywords
    MOSFET; semiconductor device testing; W/L geometry; layout area; mismatch; submicron MOS transistors; test structure; Circuit testing; Cities and towns; Educational institutions; Geometry; Intrusion detection; MOS devices; MOSFET circuits; Microelectronics; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
  • Conference_Location
    Trento
  • Print_ISBN
    0-7803-2783-7
  • Type

    conf

  • DOI
    10.1109/ICMTS.1996.535619
  • Filename
    535619
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2711832