Title :
On matching properties and process factors for submicrometer CMOS
Author :
Wong, Shyh-Chyi ; Pan, Kuo-Hua ; Ma, Dye-Jyun ; Liang, M.S. ; Tseng, P.N.
Author_Institution :
Dept. of Electron. Eng., Feng Chia Univ., Taichung, Taiwan
Abstract :
Matching property of a 0.5 μm CMOS process is investigated. Short channel effect in matching is studied by incorporating source and drain parasitic resistance, which contributes significantly to high-gate-bias mismatch. In characterizing matching statistics, it is found that long-spacing mismatch, due to process gradients, differs considerably from short-spacing mismatch. Threshold voltage mismatch is proportional to (WL)-0.75 due to local edge variations. In addition, a n0.5-law model is developed to model the stripe-layout mismatch
Keywords :
CMOS integrated circuits; 0.5 micron; matching statistics; parasitic resistance; power law model; process factors; short channel effect; stripe-layout mismatch; submicrometer CMOS; threshold voltage mismatch; Analog circuits; CMOS process; Circuit testing; Equations; Immune system; Integrated circuit modeling; Predictive models; Semiconductor device measurement; Semiconductor device modeling; Threshold voltage;
Conference_Titel :
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location :
Trento
Print_ISBN :
0-7803-2783-7
DOI :
10.1109/ICMTS.1996.535620
