Self-heating and its implications on hot carrier reliability evaluations

Author

Mittl, Steven ; Guarin, Fernando

Author_Institution

Microelectron. Div., IBM Corp., Essex Junction, VT, USA

fYear

2015

fDate

19-23 April 2015

Abstract

Device level Self-Heating (SH) is becoming a limiting factor during traditional DC Hot Carrier stresses in bulk and SOI technologies. Consideration is given to device layout and design for Self-Heating minimization during HCI stress in SOI technologies, the effect of SH on activation energy (Ea) and the SH induced enhancement to degradation. Applying a methodology for SH temperature correction of extracted device lifetime, correlation is established between DC device level stress and AC device stress using a specially designed ring oscillator.

Keywords

MOSFET; heating; hot carriers; integrated circuit reliability; silicon-on-insulator; DC hot carrier stress reliability evaluations; SH induced enhancement; SH temperature correction; SOI technology; activation energy; bulk FinFET technology; device design; device layout; device level self-heating minimization; device lifetime extraction; limiting factor; ring oscillator; silicon-on-insulator; Degradation; Human computer interaction; Logic gates; Ring oscillators; Stress; Temperature distribution; Temperature measurement; Activation Energy; FINFET; Hot Carriers; SOI; Self-Heating;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112726

Filename

7112726