DocumentCode
2712292
Title
Multi-cell soft errors at the 16-nm FinFET technology node
Author
Tam, N. ; Bhuva, B.L. ; Massengill, L.W. ; Ball, D. ; McCurdy, M. ; Alles, M.L. ; Chatterjee, I.
Author_Institution
Marvell Semicond., San Jose, CA, USA
fYear
2015
fDate
19-23 April 2015
Abstract
Soft error performance of 16-nm FinFET SRAM designs fabricated using a commercial bulk CMOS process is evaluated using heavy-ions. Results included supply voltage variations show that multi-cell upsets dominate soft-error rates. Dual-port SRAM has higher cross-section than single-port SRAM but did not have any multi-cell upset across the bit-line direction. TCAD simulations showing the extent of the perturbation in the electric parameters as a function of particle LET support the experimental data.
Keywords
CMOS integrated circuits; SRAM chips; integrated circuit design; radiation hardening (electronics); FinFET SRAM designs; FinFET technology node; TCAD simulations; bit-line direction; commercial bulk CMOS process; dual-port SRAM; heavy-ions; multicell soft errors; multicell upsets; particle LET; single-port SRAM; size 16 nm; supply voltage variations; Capacitance; Electric potential; Error correction codes; FinFETs; SRAM cells; FinFET technology; SRAM; TCAD modeling; multi-bit upsets; scaling; soft errors;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location
Monterey, CA
Type
conf
DOI
10.1109/IRPS.2015.7112730
Filename
7112730
Link To Document