A highly reliable DRAM 3-D wafer thinning process

The mechanical properties of silicon substrate begin to deteriorate with the wafer thinning process particularly when thicknesses approach 50um or below. Key mechanical indexes such as Young´s modulus, hardness and fracture toughness are characterized by nanoindentation method to study the impact of thinning wafers on critical electrical parameters. It has been published that the lattice structure of Si substrate becomes highly distorted for wafer thicknesses below 50um. Depending on the magnitude of this distortion in the lattice structure, a reduction in Young´s modulus is generally observed. However, we demonstrate a thinning process that shows minimal impact on device reliability.