A Novel Approach of Synthesizing Low Power VLSI Architecture

With the leaps and bounds progression of VLSI technol- ogy, the requirement of low power VLSI architecture has become highly on demand, specially for hand-held, bat- tery driven, portable applications. In this paper we have identified several low power strategies and applied them to realize a low power VLSI architecture suitable for motion estimation block in a video codec chip. For motion estima- tion we have adopted the TBHEX block matching algorithm [14]. Our proposed architecture has been synthesized with the Synopsis Design Analyzer tool and experimental results reveal that it requires only 22.14 mW power. Further our proposed architecture is area efficient with 30 K gate counts including memory within the chip boundary.