Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer

It has always been assumed all along that the percolation path in the high-κ (HK) and interfacial layer (IL) of dual layer dielectric stacks are perfectly aligned with each other. There is however no solid evidence to date to support this assumption because the standard stress levels applied and compliance chosen for time dependent dielectric breakdown (TDDB) tests is high enough to instantaneously rupture both the HK and IL layers, once one of them reaches the percolation stage of degradation. The aim of this study is to probe the location of the HK and IL percolation paths and study their correlation by means of a novel TDDB test algorithm that enables a finite time two-stage event of BD for the dual layer stack with only one dielectric percolating during each stage of stress. The analysis reveals that although in most cases the HK and IL layers have the BD location very close to each other, there are cases of slight misalignment that can be advantageous from a reliability viewpoint as misaligned percolation paths result in a much lower leakage current (even in the logarithmic scale) as compared to the perfectly aligned ones. We also extend this analysis to probing the locations of different stress induced leakage current (SILC) defect clusters in the dielectric prior to any breakdown event.