A two-differential-input/differential-output fully complementary self-biased open-loop analog voltage comparator in 40 nm LP CMOS

A novel fully complementary and fully differential open-loop comparator topology, that consists of a two-stage preamplifier cascaded with a latch, achieves a sub-100 ps propagation delay for a 50 mV_pp input signal amplitude under 1.1 V supply and 2.1 mW power consumption. The comparator features two differential pairs of inputs and is truly self-biased through a negative feedback loop thereby eliminating the need for a voltage reference and suppressing the influence of process, supply voltage and temperature variations. Proposed comparator occupies 0.001 mm² in 40 nm LP CMOS process.