Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing

Author

Randriamihaja, Y. Mamy ; McMahon, W. ; Balasubramanian, S. ; Nigam, T. ; Parameshwaran, B. ; Mann, R. ; Klick, T. ; Schaefer, T. ; Kumar, A. ; Song, Y. ; Joshi, V. ; Ranjan, R. ; Chen, F.

Author_Institution

GLOBALFOUNDRIES, Malta, NY, USA

fYear

2015

fDate

19-23 April 2015

Abstract

Extended 6 Transistors (6T) SRAM (Static Random-Access Memory) characterization is used to measure degradation while separating intrinsic from extrinsic yield and accounting for yield assessment challenges such as voltage drop and measurement variability. Separation of extrinsic yield pre- and post-stress reveals weak yield fixes and reduces HTOL (High Temperature Operating Life) failure risk.

Keywords

SRAM chips; failure analysis; integrated circuit reliability; integrated circuit testing; HTOL failure risk reduction; extended 6-transistor SRAM characterization; extrinsic end-of-life risk assessment; extrinsic yield post-stress; extrinsic yield pre-stress; functional SRAM wafer level testing; high-temperature operating life failure risk; intrinsic end-of-life risk assessment; measurement variability; static random-access memory; voltage drop; yield assessment; Arrays; Current measurement; Degradation; Random access memory; Stress; Temperature measurement; Voltage measurement; 6T SRAM; BTI; TDDB; reliability; yield;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112759

Filename

7112759