Analyzing path delays for accelerated testing of logic chips

Author

Ray, Emily ; Linder, Barry ; Robertazzi, Raphael ; Stawiasz, Kevin ; Weger, Alan ; Yashchin, Emmanuel ; Stathis, James ; Peilin Song

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2015

fDate

19-23 April 2015

Abstract

We develop a test methodology utilizing the critical path delay to monitor and predict the degradation of circuits during a ramp voltage stress (RVS). Stress is applied by looping functional patterns during RVS. Our results demonstrate that the degradation behavior of a functional circuit can be characterized and analyzed with RVS in a manner similar to that developed for a single transistor. This alternative fast test lends itself to in-line testing with reduced times and small sample numbers.

Keywords

CMOS logic circuits; life testing; logic testing; stress analysis; CMOS integrated circuit; RVS; accelerated testing; critical path delay; functional circuit degradation behavior; in-line testing; logic chips; looping functional patterns; path delay analysis; ramp voltage stress; single transistor; Acceleration; Degradation; Delays; Semiconductor device measurement; Stress; Stress measurement; Temperature measurement; CMOS integrated circuit; RVS; bias temperature instability; degradation; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112764

Filename

7112764