Addressing Test Challenges in Advanced Technology Nodes

As process technologies continue to shrink and design complexity grows, today´s designs present a unique set of test challenges including higher test costs, higher power consumption during test, lower design productivity and new defects at small geometries. The designs are larger and using multiple processor cores in SoCs to enable the next generation of mobile internet devices. Each core contains its own compression logic to lower test costs by reducing test application time and test data volume. But these cores all compete for chip-level test resources, limiting pin access at the core level. Techniques are therefore needed to implement architectures that make efficient use of limited test resources while maximizing test coverage and minimizing pattern count.In addition, today´s demanding video centric applications require more memory, resulting in a shift from the logic-dominant chips of the past to memory-dominant chips. Embedded memories are the densest components within a SoC, accounting for more than 50 percent of the chip area. Implemented using aggressive design rules, embedded memories tend to be more susceptible to manufacturing defects and field reliability problems than any other core on a chip. Therefore, the overall yield of an SoC depends heavily on the memory yield, and securing high memory yield is critical to achieving lower silicon cost. Embedded memory test requires solutions capable of addressing yield and reliability needs such as fault detection, repair at the manufacturing level, diagnosis for process improvement and field repair capabilities-all with minimal impact on the functional design.