Optimal Design of Active Anti-islanding Method Using Digital PLL for Grid-connected Inverters

This paper proposes the optimal design method based on NDZ analysis to secure the islanding detection ability and to maintain the stability and power quality when the grid is connected. Moreover, this paper presents the real time digital PLL (Phase Lock Loop) to eliminate the transient time instead of zero crossing based PLL. A PSiM-based model and analysis of the system is presented, specially aimed at improving the effectiveness of active frequency drift with positive feedback (AFDPF), which causes the inverter current to be generated slightly lower or higher in frequency than the frequency of the terminal voltage with frequency feedback. As a result, the proposed system is more sensitive and reliable than the conventional AFDPF method. Experimental results, on a 3 kW inverter connected to 220 V, 60 Hz utility, are discussed.