A Thermal-Driven Test Application Scheme for 3-Dimensional ICs

In this work, we propose a novel scan architecture for 3-D ICs by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-DICs often cause performance and reliability issues, we also developed a new test ordering scheme to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% by the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%.