A Probabilistic and Constraint Based Approach for Low Power Test Generation

Inserting scan chain into the circuit alongside the combinational automatic test pattern generation (ATPG) is the most commonly used test technique for digital circuits. Since power dissipation in test mode is generally much higher than in the functional mode, some considerations should be made during ATPG. This paper presents a probabilistic and constraint based approach for scan-based low power test generation. This ATPG exploits signal probability analysis to estimate fault detection probability as well as signal transition activities to guide test generation process. The effectiveness of the proposed approach has been evaluated by applying it to ISCAS85 and ISCAS89 benchmarks with three different power constraints, including propagation, capture, and shift.