Title :
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods
Author :
Gharehbaghi, Amir Masoud ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper presents a method for automatic diagnosis and correction of design bugs in processors. Given a golden sequential instruction-set architecture model of a processor and its erroneous detailed cycle-accurate model at micro-architecture level, we employ a symbolic simulator and a property checker in an iterative process to formally find the candidate buggy locations and their corresponding fixes, without requiring an error model. We have shown the effectiveness of our method on a complex out-of-order super scalar processors supporting atomic execution.
Keywords :
error correction; fault diagnosis; instruction sets; logic design; microprocessor chips; automatic design bug correction; automatic design bug diagnosis; complex out-of-order super scalar processors; complex processors; cycle-accurate model; error model free automatic design error correction; formal methods; golden sequential instruction-set architecture model; iterative process; microarchitecture level; property checker; symbolic simulator; Computer bugs; Error correction; Logic gates; Multiplexing; Program processors; Radiation detectors; Registers; design error correction; design error diagnosis; formal verification; micro architecture debugging; processors;
Conference_Titel :
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location :
Niigata
Print_ISBN :
978-1-4673-4555-2
Electronic_ISBN :
1081-7735
DOI :
10.1109/ATS.2012.44
