Title :
Asymmetry and mismatch in CMOSFETs with source/drain regions fabricated by various ion-implantation methods
Author :
Ohzone, Takashi ; Miyakawa, Tetsu ; Yabu, Toshiki ; Odanaka, Shinji
Author_Institution :
Dept. of Electron. & Inf., Toyama Univ., Japan
Abstract :
Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5 μm surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated by four ion-implantation methods and designed by a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry. There is not a single choice that simultaneously satisfies the minimum average and deviation values of A&M for all electrical parameters. For minimizing A&M in (ID and β), (VT and S) and IB, n- and p-MOSFETs fabricated by 7°×4-implantation, n-MOSFETs with 0°- and 7°×4-implantation, and n- and p-MOSFETs with 0°- and 7°×4-implantation are recommended, respectively. However 0°-implanted MOSFETs must not be used because of their inferior punchthrough characteristics
Keywords :
CMOS analogue integrated circuits; MOSFET; ion implantation; 0.5 micron; CMOSFETs; NMOSFET; PMOSFET; asymmetry characteristics; buried-channel p-MOSFETs; conventional layout; drain region fabrication; ion implantation methods; mismatch characteristics; side-by-side layout; source region fabrication; source/drain asymmetry; surface-channel n-MOSFETs; Analog circuits; CMOS process; CMOSFET circuits; Design methodology; Electric variables; Informatics; MOSFET circuits; Random access memory; Testing; Threshold voltage;
Conference_Titel :
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location :
Trento
Print_ISBN :
0-7803-2783-7
DOI :
10.1109/ICMTS.1996.535640
