A Scan-Out Power Reduction Method for Multi-cycle BIST

High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops´ values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage.