A simulation study for very low power 5 GHz CMOS voltage-controlled oscillators and frequency dividers

Author

AyÖz, Suat ; Wassell, Ian J. ; Udrea, Florin

Author_Institution

Dept. of Eng., Cambridge Univ., UK

Volume

1

fYear

2004

fDate

4-6 Oct. 2004

Lastpage

144

Abstract

Capability of a deep sub-micron bulk CMOS process for low power RF applications is investigated. Very low power 5 GHz voltage-controlled oscillator and 2:1 frequency divider simulations are presented using a 0.18 μm bulk CMOS process. The VCO uses NMOS varactors and tunes between 4.9 GHz and 6.1 GHz with a phase noise of 108.5 dBc/Hz at 1 MHz offset while drawing 490 μA from a 1.8 V power supply. The 2:1 frequency divider is operational up to 6.7 GHz with only 100-mV peak input signal level. Divider operates with a 1-V power supply drawing only 670 μA.

Keywords

CMOS analogue integrated circuits; MOS integrated circuits; circuit simulation; frequency dividers; low-power electronics; varactors; voltage-controlled oscillators; 0.18 micron; 1 V; 1.8 V; 100 mV; 490 muA; 5 GHz; 670 muA; CMOS; NMOS varactors; deep sub-micron process; frequency dividers; low-power RF applications; peak input signal level; phase noise; power supply; very low power VCO; voltage-controlled oscillators; Capacitance; Circuit noise; Circuit simulation; Energy consumption; Frequency conversion; MOS devices; Noise figure; Power engineering and energy; Power supplies; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International

Print_ISBN

0-7803-8499-7

Type

conf

DOI

10.1109/SMICND.2004.1402824

Filename

1402824