A Space Vector PWM Scheme to Reduce Common Mode Voltage for a Cascaded Multilevel Inverter

Author

Gupta, Amit Kumar ; Khambadkone, Ashwin M.

Author_Institution

Nat. Univ. of Singapore

fYear

2006

fDate

18-22 June 2006

Firstpage

1

Lastpage

7

Abstract

Multilevel inverters generate common mode voltage similar to two-level inverters. Schemes have been reported for multilevel inverters to reduce the common mode voltage. However, most of the schemes result in reduced modulation depth, high switching losses and high harmonic distortion. This paper proposes a simple space vector PWM scheme to reduce common mode voltage for cascaded multilevel inverter and addresses these issues. The scheme is explained for 5-level inverter. The scheme can be easily extended to a n-level inverter. Both experimental and simulation results are provided

Keywords

PWM invertors; harmonic distortion; losses; cascaded multilevel inverter; common mode voltage reduction; high harmonic distortion; high switching losses; modulation depth reduction; space vector PWM scheme; two-level inverters; AC motors; Electromagnetic interference; Hardware; Harmonic distortion; Leg; Pulse width modulation inverters; Shafts; Space vector pulse width modulation; Switching loss; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialists Conference, 2006. PESC '06. 37th IEEE

Conference_Location

Jeju

ISSN

0275-9306

Print_ISBN

0-7803-9716-9

Type

conf

DOI

10.1109/PESC.2006.1712035

Filename

1712035