Parametric test engineering optimization: methodology and software system

Author

D´Ouville, ThierryTernisien ; Mendez, France ; Bruines, Joop ; Zangara, Louis ; Durieu, Guy

Author_Institution

Centre Commun CNET SGS-Thomson, Crolles, France

fYear

1996

fDate

25-28 Mar 1996

Firstpage

185

Lastpage

189

Abstract

To improve drastically the productivity and the quality of parametric testing, we have defined a new design methodology based on a global and concurrent approach. A CAD system has been developed allowing the automatic generation of all the parametric test tools and the secured transfer of all information about the test chip to the parametric tester. This CAD solution has been progressively implemented in the Centre Commun CNET SGS-Thomson to design the test chips for CMOS 0.5 μm, CMOS 0.35 μm and BiCMOS technologies. Global indicators confirm the productivity and quality improvement of the parametric test design process

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; automatic test software; automatic testing; circuit CAD; circuit optimisation; design for testability; graphical user interfaces; integrated circuit design; integrated circuit testing; 0.35 micron; 0.5 micron; BiCMOS technology; CAD system; CMOS technologies; PILOT Station; automatic test tool generation; design methodology; parametric test engineering optimization; software system; Automatic testing; BiCMOS integrated circuits; CMOS technology; Design automation; Design methodology; Optimization methods; Process design; Productivity; Software testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on

Conference_Location

Trento

Print_ISBN

0-7803-2783-7

Type

conf

DOI

10.1109/ICMTS.1996.535643

Filename

535643