Title :
Design and implementation of a two-dimensional fast Fourier transform chip
Author :
Krakow, W.T. ; Batchelor, William E. ; Liu, Wentai ; Hildebrandt, Thomas ; Hughes, Thomas ; Yeh, Tong-Fei ; Salama, Roberto ; Mei, Geegwo
Author_Institution :
Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
Abstract :
The authors describe a rasterized pipelined architecture for performing a two-dimensional fast Fourier transformation (2DFFT). Incorporating over 152,000 transistors in 1.25 mu m CMOS on a 9 mu m die, the chip functions at a clock speed of 10 MHz, processing a 256*256-pixel image at a real-time frame rate of 30 Hz. The input and output data formats are rasterized streams of 22-bit fixed-point complex numbers. The authors present the chip architecture and describe the design of its constituent units. On-chip storage of the sine/cosine factors and the absence of a corner-turning memory are this design´s most novel features.<>
Keywords :
CMOS integrated circuits; computerised picture processing; fast Fourier transforms; microprocessor chips; pipeline processing; 1.25 micron; 10 MHz; 22 bits; 256 pixel; 30 Hz; 65536 pixel; 9 micron; CMOS; fixed-point complex numbers; on-chip storage; rasterized pipelined architecture; sine factors; sine/cosine factors; two-dimensional fast Fourier transform chip; CMOS process; CMOS technology; Clocks; Computer architecture; Delay; Fast Fourier transforms; Microelectronics; Pixel; Streaming media; Surveillance;
Conference_Titel :
System Theory, 1988., Proceedings of the Twentieth Southeastern Symposium on
Conference_Location :
Charlotte, NC, USA
Print_ISBN :
0-8186-0847-1
DOI :
10.1109/SSST.1988.17121
