Design and Analysis of a Fully-Distributed Parallel Packet Switch

A parallel packet switch (PPS) is a multistage switch aimed at building a very high-speed switch using much slower devices. A PPS in general has three stages. Several packet switches are placed in the central stage, which operate slower than the external line rate. Incoming packets are spread over the center-stage switches by demultiplexers at the input stage. Packets destined to each output port need to be collected and reordered if necessary at the output stage. The existing designs of PPS suffer from high algorithmic complexity and high-speed buffer requirement. In this paper, we have proposed a fully distributed algorithm for demultiplexer with minimal complexity of O(1). Besides the buffers in the proposed architecture operates at the low internal link rate. We show that our design is stable and its performance is comparable to the existing designs. The resulting PPS architecture is more simple and implementable using both optical and electrical components