Title :
LDS-ATPG: an automatic test pattern generation system for combinational VLSI circuits
Author :
Jiang, Sen-Chung ; Lee, Chung Len ; Shen, Wen-Zen ; Chen, Jwu-E ; Wu, Ching-Ping
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Abstract :
An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times
Keywords :
VLSI; automatic testing; combinatorial circuits; integrated logic circuits; logic testing; ACCEPT; DISRUPT; LDS-ATPG; SLOPE1; automatic test pattern generation system; combinational VLSI circuits; deterministic test pattern generator; dynamic compaction; fault coverage; fault simulator; linear feedback shift register; pseudorandom pattern generator; random pattern generator; test pattern generators; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Controllability; Linear feedback shift registers; Test pattern generators; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68604
