Title :
Minimizing the Output Voltage Ripple of a DC/DC Power Converter by Phase Locking
Author :
Upadhyaya, Prabal ; Hess, Herbert L.
Author_Institution :
Mieroelectronics Research and Communications Institute (MRCI), Department of Electrical and Computer Engineering, University of Idaho, Moscow, Idaho 83844, Prabal.upadhyaya@vandals.uidaho.edu
Abstract :
Reduced passives size and improved quality factor (Q) for an on-chip inductor can be achieved in a fully integrated DC/DC power converter by high frequency switching. This paper presents a high speed closed-loop buck converter that uses phase locking control system to reduce output voltage ripple. A closed-loop DC/DC power converter has been designed in a TSMC-0.25¿m technology. The power converter takes a 3.3 V DC input and switches at 1.02 GHz to produce output voltage of 1.5 V and 1.8 V DC and stabilizes in less than 600 ns. Design equations and simulation results are presented.
Keywords :
Buck converters; Capacitors; Frequency conversion; Inductors; Pulse width modulation; Pulse width modulation converters; Q factor; Switches; Switching converters; Voltage; On-chip DC/DC power Converter; high frequency; phase locking;
Conference_Titel :
Microelectronics and Electron Devices, 2007. WMED 2007. IEEE Workshop on
Conference_Location :
Boise, ID, USA
Print_ISBN :
1-4244-1114-9
Electronic_ISBN :
1-4244-1114-9
DOI :
10.1109/WMED.2007.368052
