DocumentCode
2715644
Title
Automatic test chip documentation synthesis
Author
Nagorski, Walter ; McGee, William ; Piccioli, Ellen G. ; Bair, Lawrence A.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1996
fDate
25-28 Mar 1996
Firstpage
221
Lastpage
225
Abstract
We describe a new test chip documentation methodology which simultaneously generates inputs for layout design and test chip documentation. On-line test chip documentation is generated based on specifications from the test structure requester/designer. This specification is used as input for both the layout designer and also for software which generates on-line test structure documentation. In addition, results from layout and circuit verification tools are compared with specifications to ensure that layout, specification, and documentation agree
Keywords
automatic testing; integrated circuit layout; integrated circuit testing; system documentation; automatic test chip documentation synthesis; circuit layout design; on-line testing; software; specification; verification; Automatic testing; Circuit testing; Design engineering; Documentation; Markup languages; Productivity; Software testing; Standardization; Standards development; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location
Trento
Print_ISBN
0-7803-2783-7
Type
conf
DOI
10.1109/ICMTS.1996.535650
Filename
535650
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