An Efficient Simulated Annealing Based VLSI Floorplanning Algorithm for Slicing Structure

Floor planning is one of the most crucial stages in VLSI circuit design. Slicing structure is a simple and efficient floor plan representation. The orientation of modules has a significant impact on the performance (e.g., area) of a chip for slicing floor plan. At first, the reason which causes dead space is analyzed and an intuitive and fast approach is proposed to determine the reasonable orientation of each module. Then, a perturbing operator of normalized polish expression is modified to generate neighborhood solution, and simulated annealing algorithm is used to search for the optimal floor plan solution. Experimental results indicate that our developed algorithm achieves promising area utilization on the commonly used MCNC benchmark circuits.