A low-noise parasitic-insensitive switched-capacitor CMOS interface circuit for MEMS capacitive sensors

This paper describes a differential low-noise high-resolution parasitic-insensitive switched-capacitor readout circuit that is intended for capacitive sensors, in particular, for MEMS inertial sensory systems. The operation of the proposed readout front-end circuit is explained. Amplitude modulation/demodulation and correlated double sampling techniques are used in the interface circuit to minimize the undesirable effects of the amplifier offset and flicker (1/f) noise. The application of the aforementioned techniques also further improve the sensitivity of the readout circuit. The interface system is designed and laid out in a 0.8 μm CMOS process. Post-layout simulation results demonstrate that the circuit is capable of resolving input sense capacitance variations as low as 0.5 aF with a sensitivity of 9.98 mV/aF. The circuit consumes 8.38 mW from a single 5 V supply.