Accurate extraction of inductively-affected delay using an optimized tapered partitioning scheme for global interconnects

The delay caused by global interconnects plays a critical role in the performance of VLSI circuits, particularly for transmission effects in nano scales. This paper presents an analytical formulation for the delay of tapered partitioning scheme of buffer insertion in long global interconnects. The inductive effects have been taken into account in RLC delay expressions. Because of complexity of the expressions and various design parameters simulated annealing has been used to extract accurate optimum values for the parameters. Using this method, we have achieved 60% improvement in the delay reduction.