Highly Integrated 60 GHz-band x12 Multiplier MMIC

This paper presents a 60 GHz-band times12 multiplier MMIC. The multiplier consists of a quadrupler and a following tripler. In order to integrate them in a single chip with a size of 2.5 mm times 1.15 mm, lumped elements are adopted for matching and suppression circuits. A capacitor is introduced between fundamental and 2^nd harmonic suppression stubs of a quadrupler so as to improve the suppression level. The fabricated multiplier exhibits an output power of higher than 0 dBm from 58 to 63 GHz with an input power of -5 dBm. The adjacent 11 ^th and 13^th harmonic suppressions are larger than 20 dBc at a center frequency of 60.6 GHz. The multiplier is also mounted in an LTCC package using a flip-chip bonding technique. The flipped multiplier shows a decrease of 4 dB in the output power in the temperature range from -20 to 80 degC. As far as the authors know, this is the first times12 FET-multiplier MMIC in a millimeter-wave band