Title :
Architecture design of MPEG-2 decoder system
Author :
Lee, Yung-Pin ; Chen, Liang-Gee ; Ku, Chung-Wei
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An architecture for the VLSI design of an MPEG-2 video decoder is introduced to achieve the MP@ML (main profile, main level). The hardware complexity is analyzed, and the decoding unit is designed to reach the required performance. The decoding unit includes variable length decoding (VLD), inverse scan, inverse quantization (IQ), IDCT, and motion compensation
Keywords :
VLSI; code standards; decoding; discrete cosine transforms; motion compensation; quantisation (signal); telecommunication standards; video coding; video equipment; IDCT; MPEG-2 decoder system; MPEG-2 video decoder; VLSI design; architecture design; decoding unit; hardware complexity; inverse quantization; inverse scan; main level; main profile; motion compensation; performance; variable length decoding; Bit rate; Buffer storage; Decoding; Delay; HDTV; Hardware; Notice of Violation; Random access memory; Scalability; Transform coding;
Conference_Titel :
Consumer Electronics, 1995., Proceedings of International Conference on
Conference_Location :
Rosemont, IL
Print_ISBN :
0-7803-2140-5
DOI :
10.1109/ICCE.1995.517978
