• DocumentCode
    2716505
  • Title

    Operation scheduling considering time borrowing for high-performance latch-based circuits

  • Author

    Inoue, Keisuke ; Kaneko, Mineo

  • Author_Institution
    Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol. (JAIST), Nomi, Japan
  • fYear
    2011
  • fDate
    26-29 June 2011
  • Firstpage
    245
  • Lastpage
    248
  • Abstract
    Recently, latch-based design has attracted attention due to its several merits. Time borrowing is one feature of latches, where a slower functional unit can borrow timing slacks from a faster functional unit. This paper shows that latency can be reduced by integrating the time borrowing into operation scheduling in latch-based design. Specifically, continuous execution delay model is adapted to operation scheduling, and design conditions based on this model are presented. A list scheduling-based algorithm is proposed to solve the minimum-latency resource-constrained scheduling problem. Experiments demonstrate the latency reduction with an average of 11% compared to the conventional design.
  • Keywords
    VLSI; delays; logic circuits; network synthesis; continuous execution delay model; high-performance latch-based circuits; latency; operation scheduling; time borrowing; very large scale integration; Clocks; Delay; Job shop scheduling; Latches; Processor scheduling; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International
  • Conference_Location
    Bordeaux
  • Print_ISBN
    978-1-61284-135-9
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2011.5981301
  • Filename
    5981301