Title :
An 8Gsps, 65nm CMOS wideband track-and-hold
Author :
Mattos, D. ; Hellmuth, P. ; Recoquillon, C. ; Gauffre, S. ; Caïs, P. ; Pedroza, J.-L. ; Bégueret, J-B ; Baudry, A.
Author_Institution :
IMS Lab., Univ. of Bordeaux, Talence, France
Abstract :
A track-and-hold (T&H) circuit has been designed and fabricated using the 65 nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a -3 dB input bandwidth wider than 8 GHz. At 8 GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178 mW and 0 dB, respectively. The T&H core dissipates around 40 mW. The measured total harmonic distortion (THD) at Nyquist sampling conditions is about -37 dB. The circuit die area is 1.1 mm2.
Keywords :
CMOS integrated circuits; harmonic distortion; sample and hold circuits; CMOS wideband track-and-hold circuit; Nyquist sampling conditions; STMicroelectronics; THD; frequency 8 GHz; gain -3 dB; gain 0 dB; power 178 mW; power 40 mW; power consumption; size 65 nm; total harmonic distortion; Bandwidth; CMOS integrated circuits; CMOS technology; Capacitors; Clocks; Impedance matching; Power demand; ADC; CMOS; track-and-hold; wideband operation;
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International
Conference_Location :
Bordeaux
Print_ISBN :
978-1-61284-135-9
DOI :
10.1109/NEWCAS.2011.5981320
