Performance evaluation of Physically Unclonable Function by delay statistics

This paper presents a novel approach to evaluate silicon Physically Unclonable Functions (PUFs) implemented in FPGAs and based on delay elements. The metrics studied to characterize the PUFs are Randomness, Uniqueness and Steadiness. They take advantage of the measured physical values of elementary component making up the PUF. The delay distributions provide the interest to quantify the PUF at the physical level rather than carrying out a lot of experiments to get the PUF IDs at logical level. An Arbiter PUF composed of identical chains has been considered as a test chip to evaluate the method with the proposed metrics. Experiments have been carried out on CYCLONE II FPGA and the corresponding results shows the intra-device performance of the studied PUF.