DocumentCode :
2716857
Title :
Security challenges during VLSI test
Author :
Hély, David ; Rosenfeld, Kurt ; Karri, Ramesh
Author_Institution :
LCIS, Grenoble Inst. of Technol., Valence, France
fYear :
2011
fDate :
26-29 June 2011
Firstpage :
486
Lastpage :
489
Abstract :
VLSI testing is a practical requirement, but unless proper care is taken, features that enhance testability can reduce system security. Data confidentiality and intellectual property protection can be breached through testing security breaches. In this paper we review testing security problems, focusing on the scan technique. We then present some countermeasures which have recently been published and we discuss their characteristics.
Keywords :
VLSI; integrated circuit testing; security; VLSI testing; scan technique; system security reduction; Built-in self-test; Cryptography; Protocols; System-on-a-chip; Watermarking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International
Conference_Location :
Bordeaux
Print_ISBN :
978-1-61284-135-9
Type :
conf
DOI :
10.1109/NEWCAS.2011.5981325
Filename :
5981325
Link To Document :
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