Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel

Author

Nedjah, Nadia ; De Macedo Mourelle, Luiza

Author_Institution

Dept. of de Syst. Eng. & Comput., State Univ. of Rio de Janeiro, Brazil

fYear

2002

fDate

2002

Firstpage

3

Lastpage

8

Abstract

Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time×area classic factor.

Keywords

circuit analysis computing; field programmable gate arrays; iterative methods; public key cryptography; sequential circuits; systolic arrays; FPGA prototype; Montgomery modular multiplication; Parallel architecture; RSA cryptosystem; architecture systolic array-based architecture; fast Montgomery algorithm; hardware implementations; iterative sequential architecture; operand size; operation time; public-key cryptography systems; Algorithm design and analysis; Computer architecture; Concurrent computing; Field programmable gate arrays; Hardware; Iterative algorithms; Prototypes; Public key; Public key cryptography; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137629

Filename

1137629