A new architecture for 2´s complement Gray encoded array multiplier

We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a hybrid encoding for the architecture, which is a compromise between the minimal input dependency presented by binary encoding and the low switching characteristic of the Gray encoding. We have experimented using the Gray code for each group of m bits, thus potentially further reducing the switching activity both internally and at the inputs. The architecture is extended for radix-2^m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. The flexibility of our architecture allows for the easy construction of multipliers for different values of m. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the modified Booth multiplier.