Architectural synthesis of finite impulse response digital filters

Author

Mehler, Ronald W. ; Zhou, Dian

Author_Institution

Texas Univ., Dallas, TX, USA

fYear

2002

fDate

2002

Firstpage

20

Lastpage

25

Abstract

A system for developing digital fillers at a higher level of abstraction than any currently in use is presented. Based on the principle that architectural tradeoffs can be quantified and thus automated, the synthesizer can determine the architecture that best suits the application, allowing unprecedented productivity by engineers while producing high quality circuits. Comparisons are made between filters generated with architectural synthesis and those hand coded and synthesized with the Synopsys module compiler and others made using common platforms.

Keywords

FIR filters; digital filters; hardware description languages; high level synthesis; integrated circuit design; integrated circuit modelling; FIR digital filter architectural synthesis; FiG filter generator; Synopsys module compiler hand coded/synthesized filters; Verilog HDL descriptions; architectural synthesis design methodology paradigm; filter synthesizer; finite impulse response digital filters; high abstraction level filter design; quantified/automated architectural tradeoffs; Adders; Circuit synthesis; Digital filters; Finite impulse response filter; Hardware design languages; Integrated circuit synthesis; Logic circuits; Productivity; Registers; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137632

Filename

1137632